050-7002 rev d 7-2010 maximum ratings all ratings: t c = 25c unless otherwise speci ? ed. static electrical characteristics bll sll apt10090bll apt10090sll 1000v 12a 0.950 lower input capacitance increased power dissipation lower miller capacitance easier to drive lower gate charge, qg to-247 or surface mount d 3 pak package power mos 7 ? is a new generation of low loss, high voltage, n-channel enhancement mode power mosfets. both conduction and switch-ing losses are addressed with power mos 7 ? by signi ? cantly lowering r ds(on) and q g . power mos 7 ? combines lower conduction and switching losses along with exceptionally fast switching speeds inherent with apt's patented metal gate structure. power mos 7 mosfet caution: these devices are sensitive to electrostatic discharge. proper handling procedures should be followed. microsemi website - http://www.microsemi.com to-247 d 3 pak g d s symbol parameter apt10090 unit v dss drain-source voltage 1000 volts i d continuous drain current @ t c = 25c 12 amps i dm pulsed drain current 1 48 v gs gate-source voltage continuous 30 volts v gsm gate-source voltage transient 40 p d total power dissipation @ t c = 25c 298 watts linear derating factor 2.4 w/c t j ,t stg operating and storage junction temperature range -55 to 150 c t l lead temperature: 0.063" from case for 10 sec. 300 i ar avalanche current 1 (repetitive and non-repetitive) 12 amps e ar repetitive avalanche energy 1 30 mj e as single pulse avalanche energy 4 1210 symbol characteristic / test conditions min typ max unit bv dss drain-source breakdown voltage (v gs = 0v, i d = 250 a) 1000 volts i d(on) on state drain current 2 (v ds > i d(on) x r ds(on) max, v gs = 10v) 12 amps r ds(on) drain-source on-state resistance 2 (v gs = 10v, 6a) 0.95 ohms i dss zero gate voltage drain current (v ds = 1000v, v gs = 0v) 100 a zero gate voltage drain current (v ds = 800v, v gs = 0v, t c = 125c) 500 i gss gate-source leakage current (v gs = 30v, v ds = 0v) 100 na v gs(th) gate threshold voltage (v ds = v gs , i d = 1ma) 3 5 volts downloaded from: http:///
dynamic characteristics apt10090bll - sll 050-7002 rev d 7-2010 characteristic / test conditions continuous source current (body diode) pulsed source current 1 (body diode) diode forward voltage 2 (v gs = 0v, i s = -i d 12a ) reverse recovery time (i s = -i d 12a , dl s /dt = 100a/ s) reverse recovery charge (i s = -i d 12a , dl s /dt = 100a/ s) peak diode recovery dv / dt 5 unit amps volts ns c v/ns min typ max 12 48 1.3 700 9.0 10 symbol r jc r ja min typ max 0.42 40 unit c/w characteristicjunction to case junction to ambient symbol i s i sm v sd t rr q rr dv / dt symbol c iss c oss c rss q g q gs q gd t d(on) t r t d(off) t f e on e off e on e off characteristicinput capacitance output capacitance reverse transfer capacitance total gate charge 3 gate-source charge gate-drain ("miller ") charge turn-on delay time rise time turn-off delay time fall time turn-on switching energy 6 turn-off switching energy turn-on switching energy 6 turn-off switching energy test conditions v gs = 0v v ds = 25v f = 1 mhz v gs = 10v v dd = 500v i d = 12a @ 25c resistive switching v gs = 15v v dd = 500v i d = 12a @ 25c r g = .6 inductive switching @ 25c v dd = 670v, v gs = 15v i d = 12a, r g = 5 inductive switching @ 125c v dd = 670v v gs = 15v i d = 12a, r g = 5 min typ max 1969 332 55 71 12 47 9 5 23 4 334 77 672 100 unit pf nc ns j source-drain diode ratings and characteristics thermal characteristics 1 repetitive rating: pulse width limited by maximum junction temperature 2 pulse test: pulse width < 380 s, duty cycle < 2% 3 see mil-std-750 method 3471 4 starting t j = +25c, l = 16.81mh, r g = 25 , peak i l = 12a 5 dv / dt numbers re ? ect the limitations of the test circuit rather than the device itself. i s - i d 12a di / dt 700a/ s v r v dss t j 150 c 6 eon includes diode reverse recovery measured in accordance wtih jedec standard jesd24-1. see ? gures 18, 20. microsemi reserves the right to change, without notice, the speci ? cations and information contained herein. single pulse z jc , thermal impedance (c/w) 10 -5 10 -4 10 -3 10 -2 10 -1 1.0 rectangular pulse duration (seconds) figure 1, maximum effective transient thermal impedance, junction-to-case vs pulse duration 0.450.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.5 0.1 0.3 0.7 0.9 0.05 peak t j = p dm x z jc + t c duty factor d = t 1 / t 2 t 2 t 1 p dm note: downloaded from: http:///
050-7002 rev d 7-2010 apt10090bll - sll typical performance curves 5v 5.5v 6v 6.5 v gs =15,10v& 7.5v 7v t j = +125c t j = +25c t j = -55c v gs =10v v gs =20v v ds > i d (on) x r ds(on) max. 250 sec. pulse test @ <0.5 % duty cycle r ds(on) , drain-to-source on resistance i d , drain current (amperes) i d , drain current (amperes) (normalized) v gs(th) , threshold voltage bv dss , drain-to-source breakdown r ds(on) , drain-to-source on resistance i d , drain current (amperes) (normalized) voltage (normalized) normalized to v gs = 10v @ i d = 6a 3025 20 15 10 50 1210 86 4 2 0 2.52.0 1.5 1.0 0.5 0.0 v ds , drain-to-source voltage (volts) figure 2, low voltage output characteristics v gs , gate-to-source voltage (volts) i d , drain current (amperes) figure 3, transfer characteristics figure 4, r ds(on) vs drain current t c , case temperature (c) t j , junction temperature (c) figure 5, maximum drain current vs case temperature figure 6, breakdown voltage vs temperature t j , junction temperature (c) t c , case temperature (c) figure 7, r ds(on) vs. temperature figure 8, threshold voltage vs temperature 0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 8 0 5 10 15 20 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 3025 20 15 10 50 1.401.30 1.20 1.10 1.00 0.90 0.80 1.15 1.10 1.05 1.00 0.95 0.90 0.85 1.21.1 1.0 0.9 0.8 0.7 0.6 i d = 6a v gs = 10v downloaded from: http:///
apt10090bll - sll 050-7002 rev d 7-2010 typical performance curves v ds , drain-to-source voltage (volts) v ds , drain-to-source voltage (volts) figure 9, maximum safe operating area figure 10, capacitance vs drain-to-source voltage q g , total gate charge (nc) v sd , source-to-drain voltage (volts) figure 11, gate charge vs gate-to-source voltage figure 12, source-drain diode forward voltage v gs , gate-to-source voltage (volts) i d , drain current (amperes) i dr , reverse drain current (amperes) c, capacitance (pf) 1 10 100 1000 0 10 20 30 40 50 0 10 20 30 40 50 60 70 80 90 100 0.3 0.5 0.7 0.9 1.1 1.3 1.5 v ds =500v v ds =200v v ds =800v i d = 12a t j =+150c t j =+25c c rss c iss c oss i d (a) i d (a) figure 13, delay times vs current figure 14, rise and fall times vs current i d (a) r g , gate resistance (ohms) figure 15, switching energy vs current figure 16, switching energy vs. gate resistance v dd = 670v r g = 5 w t j = 125c l = 100 h t d(on) t d(off) e on e off e on e off t r t f switching energy ( m j) t d(on) and t d(off) (ns) switching energy ( m j) t r and t f (ns) 10,000 1,000 100 10 200100 10 1 5 10 15 20 0 5 10 15 20 5 10 15 20 0 5 10 15 20 25 30 35 40 45 50 6050 40 30 20 10 0 12001000 800600 400 200 0 4030 20 10 0 12001000 800600 400 200 0 v dd = 670v r g = 5 w t j = 125c l = 100 h v dd = 670v r g = 5 w t j = 125c l = 100 h e on includes diode reverse recovery. v dd = 670v i d = 12a t j = 125c l = 100 h e on includes diode reverse recovery. 4810 1 .1 1612 84 0 10ms 1ms 100 s t c =+25c t j =+150c single pulse operation here limited by r ds (on) downloaded from: http:///
050-7002 rev d 7-2010 apt10090bll - sll typical performance curves figure 17, turn-on switching waveforms and de ? nitions figure 18, turn-off switching waveforms and de ? nitions t j = 125 c 90% t d(off) 10% 0 90% t f drain current drain voltage gate voltage switching energy 10 % t d(on) 90% 5 % 10 % t r 5 % gate voltage t j = 125 c switching energy drain current drain voltage i c d.u.t. apt15df120b v ce figure 20, inductive switching test circuit g v dd figure 19, inductive switching test circuit microsemis products are covered by one or more of u.s. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743, 7,352,045 5,283,201 5,801,417 5,648,283 7,196,634 6,664,594 7,157,886 6,939,743 7,342,262 and foreign patents. us and foreign patents pending. all rights reserved. d 3 pak package outline to-247 (b) package outline e3 100% sn plated 15.49 (.610)16.26 (.640) 5.38 (.212)6.20 (.244) 6.15 (.242) bsc 4.50 (.177) max. 19.81 (.780)20.32 (.800) 20.80 (.819)21.46 (.845) 1.65 (.065)2.13 (.084) 1.01 (.040)1.40 (.055) 3.50 (.138)3.81 (.150) 2.87 (.113)3.12 (.123) 4.69 (.185)5.31 (.209) 1.49 (.059) 2.49 (.098) 2.21 (.087)2.59 (.102) 0.40 (.016)0.79 (.031) drain drain source gate 5.45 (.215) bsc dimensions in millimeters and (inches) 2-plcs. 15.95 (.628)16.05(.632) 1.22 (.048)1.32 (.052) 5.45 (.215) bsc{2 plcs.} 4.98 (.196)5.08 (.200) 1.47 (.058) 1.57 (.062) 2.67 (.105)2.84 (.112) 0.46 (.018) {3 plcs} 0.56 (.022) dimensions in millimeters (inches) heat sink (drain)and leads are plated 3.81 (.150)4.06 (.160) (base of lead) drain(heat sink) 1.98 (.078)2.08 (.082) gate drain source 0.020 (.001)0.178 (.007) 1.27 (.050)1.40 (.055) 11.51 (.453)11.61 (.457) 13.41 (.528)13.51(.532) revised8/29/97 1.04 (.041)1.15(.045) 13.79 (.543)13.99(.551) revised 4/18/95 downloaded from: http:///
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